Reducing Energy in Instruction Caches by Using Multiple Line Buffers with Prediction
نویسندگان
چکیده
Energy efficiency plays a crucial role in the design of embedded processors especially for portable devices with its limited energy source in the form of batteries. Since memory access (either cache or main memory) consumes a significant portion of the energy of a processor, the design of fast low-energy caches has become a very important aspect of modern processor design. In this paper, we present a novel cache architecture to reduce the dynamic energy in instruction cache. Our proposed cache architecture consists of the L1 cache, multiple line buffers, and a prediction mechanism to predict which line buffer, or L1 cache to access next. We used simulation to evaluate our proposed architecture and to compare it with the HotSpot cache, Filter cache, Predictive line buffer cache and Way-Halting cache. Simulation results show that our approach can reduce instruction cache energy consumption, on average, by 75% (compared to the base line architcture) without sacrificing performance
منابع مشابه
Energy efficient i-cache using multiple line buffers with prediction
Modern microprocessors dedicate a large portion of the chip area to the cache. Decreasing the energy consumption of the microprocessor, which is a very important design goal especially for small, battery powered, devices, depends on decreasing the energy consumption of the memory/cache system in the microprocessor. The authors investigate the energy consumption in caches and present a novel cac...
متن کاملUniversity Wednesday , 10 May 2000 Trace Cache
Due to unfortunate circumstances this lecture was not scribed, following are several points that I remember were brought up. If anyone has something to add please tell me. In this session we discussed three papers: Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism-describes several enhancements to the original University of Michigan view of the trace cache. Path-Based Nex...
متن کاملEnergy Efficient Cache Organizations for Superscalar Processors*
Organizational techniques for reducing energy dissipation in on–chip processor caches as well as off–chip caches have been observed to provide substantial energy savings in a technology independent manner. We propose and evaluate the use of block buffering using multiple block buffers, subbanking and bit line isolation to reduce the power dissipation within on–chip caches for superscalar CPUs. ...
متن کاملAn Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Using Early Tag Matching
Energy consumption has become an important design consideration in modern processors. Therefore, microarchitects should consider energy consumption, together with performance, when designing the cache architecture, since it is a major power consumer in a processor. This paper proposes an accurate and energy-efficient way determination (instead of prediction) technique for reducing energy consum...
متن کاملWay Memoization to Reduce Fetch Energy in Instruction Caches
Instruction caches consume a large fraction of the total power in modern low-power microprocessors. In particular, set-associative caches, which are preferred because of lower miss rates, require greater access energy on hits than direct-mapped caches; this is because of the need to locate instructions in one of several ways. Way prediction has been proposed to reduce power dissipation in conve...
متن کامل